The Reduction of Test-Time in VLIW-TTA Processors
نویسندگان
چکیده
In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper.
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